1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a substrate, in the surface of which a trench for use as an alignment mark is formed, and also relates to a semiconductor device including such a substrate.
2. Description of the Background Art
Generally, semiconductor devices are formed by a repetitive sequence of film deposition, photolithography, machining and ion implantation processes performed on a silicon substrate. To stack a plurality of patterns formed by the photolithography process in layers for formation of a semiconductor device, it is important to achieve accurate alignment of the patterns in the photolithography process repeated several times.
In many semiconductor devices, an element isolation structure such as a LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) structure is initially formed in a silicon substrate and used as an alignment mark for alignment in the photolithography process. FIG. 23 is a plan view illustrating in schematic form element isolation structures 101a and 101b for use as alignment marks, and FIG. 24 is a cross-sectional view taken along lines Axe2x80x94A indicated by arrows in FIG. 23. FIG. 23 shows the element isolation structures 101a and 101b when viewed from a direction perpendicular to the surface of a substrate 100.
As shown in FIGS. 23 and 24, the element isolation structures 101a and 101b each include a trench 102 formed in the surface of the substrate 100 and an insulation film 103 filled in the trench 102. The trench 102 of the element isolation structure 101a partitions off a generally square part of the active region of the substrate 100, and the trench 102 of the element isolation structure 101b further partitions off a generally square part of the active region of the substrate 100 partitioned off by the trench 102 of the element isolation structure 101a. FIG. 24 is a cross-sectional view of the element isolation structures 101a and 101b adopting, for example, an STI structure. Hereinafter, the element isolation structures 101a and 101b may be generically referred to as xe2x80x9celement isolation structures 101xe2x80x9d.
In the use of the aforementioned element isolation structures 101 as alignment marks, alignment becomes difficult in the following case. When, as shown in FIG. 25, a metal layer 104 is formed on the substrate 100 to cover the surface of the insulation film 103, light reflection from the metal layer 104 and a small difference in surface level between the substrate 100 and the insulation film 103 make optical detection of the alignment marks difficult. One example of the case where the metal layer 104 is formed on the substrate 100 is the case when a metal or metal silicide is adopted as a gate electrode material of a MOS transistor.
One way to avoid this problem is, as shown in FIG. 26, to use trenches 105a and 105b formed in the surface of the substrate 100 as alignment marks. The trenches 105a and 105b can be formed by etching the insulation films 103 of the element isolation structures 101 shown in FIG. 24.
By in this way using the trenches 105a and 105b as alignment marks, a sufficient difference in level of the surface of the substrate 100 can be ensured even when the metal layer 104 reflecting light is formed on the whole surface of the substrate 100 as shown in FIG. 27. This allows easy optical detection of the alignment marks. For easier detection of the alignment marks, the trenches 105a and 105b for use as alignment marks are preferably trenches of an STI structure which forms a difference in level perpendicular to the substrate rather than those of a LOCOS structure which forms a difference in level gently sloping to the substrate. Hereinafter, the trenches 105a and 105b are generically referred to as xe2x80x9ctrenches 105xe2x80x9d.
However, even the use of the trenches 105 as alignment marks has the following problem. In the photolithography process, if a resist is formed on the substrate 100 to fill the trenches 105 with the resist, depending on the relationship between a depth of the trenches 105 from the surface of the substrate 100 and a wavelength of illumination light for use in alignment mark detection, alignment marks may not be detected due to interference of the illumination light.
To eliminate this problem, Japanese Patent Application Laid-open No. 2001-52993 discloses a technique for forming both the aforementioned element isolation structures 101 and trenches 105 in the substrate 100 and then selecting either the element isolation structures 101 or the trenches 105 to be used as alignment marks at each process step.
However, either when only the trenches 105 are formed in the substrate 100 or when both the element isolation structures 101 and the trenches 105 are formed in the substrate 100 as above described, the use of the trenches 105 as alignment marks still has the following problem. If non-selective etching to the substrate 100 is performed with the surfaces of the trenches 105 exposed, the substrate 100 will be etched and thereby the shapes of the trenches 105 will be changed from their design value. Using such shape-changed trenches 105 as alignment marks causes a decrease in alignment accuracy in the subsequent photolithography process.
It is an object of the present invention to provide a technique for preventing a decrease in alignment accuracy in a photolithography process.
According to an aspect of the present invention, a method of manufacturing a semiconductor device includes the following steps (a) to (c). The step (a) is to prepare a substrate having a surface in which a first trench for use as an alignment mark is formed and on which a first film is formed, avoiding the first trench. The step (b) is to form a second film on side and bottom surfaces of the first trench. The step (c) is to selectively etch the first film using the second film as a protective film.
Using the second film as a protective film during etching of the first film prevents the side and bottom surfaces of the first trench from being etched during the etching of the first film. From this, the shape of the first trench for use as an alignment mark will never be changed, which prevents a decrease in alignment accuracy during the photolithography process.
According to another aspect of the present invention, a method of manufacturing a semiconductor device includes the following steps (a) to (c). The step (a) is to prepare a substrate, in a surface of which a trench for use as an alignment mark is formed. The step (b) is to form a gate electrode material on the substrate to cover the trench. The step (c) is to selectively etch the gate electrode material while leaving the gate electrode material formed on the trench, to selectively form a gate structure on the substrate.
Since the gate electrode material formed on the trench will not be etched, it is possible to prevents a situation in which the gate electrode material, when being selectively etched, remains in the trench. This results in prevention of a decrease in alignment accuracy during the photolithography process.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.